Datasheet
BR24G256-3
Software Reset
Software reset is executed to avoid malfunction after power ON, and during command input. Software reset has several
kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 40-(a), Figure 40-(b), Figure 40-(c)) Within the
dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be
output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Dummy clock×14
13
Start×2
SCL
SDA
Normal command
Normal command
1
2
14
Figure 40-(a). The Case of Dummy Clock×14 + START+START+ Command Input
Start
Dummy clock×9
Start
SCL
SDA
Normal command
Normal command
1
2
8
9
Figure 40-(b). The Case of START + Dummy Clock×9 + START + Command Input
Start×9
SCL
Normal command
1
2
3
7
8
9
SDA
Normal command
Figure 40-(c). START×9 + Command Input
※Start command from START input.
Acknowledge Polling
During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic
write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it
means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge
polling, next command can be executed without waiting for tWR = 5ms.
To write continuously, R/ W = 0, then to carry out current read cycle after write, slave address with R/ W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is returned.
First write command
S
T
A
R
T
S
T
A
R
T
S
S
T
A
C
K
H
A
T
A
R
T
Slave
Slave
C
K
H
Write Command
O
…
Address
Address
P
tWR
Second write command
S
T
A
R
T
S
S
T
O
P
A
C
K
L
A
C
K
L
A
C
K
H
A
C
K
L
Slave
Word
T
A
R
T
Slave
…
Data
Address
Address
Address
tWR
After completion of internal write,
ACK=LOW is returned, so input next
word address and data in succession.
Figure 41. Case to Continuous Write by Acknowledge Polling
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TSZ02201-0R2R0G100240-1-2
25.Feb.2013 Rev.002
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