Datasheet
BR24G256-3
Read Command
1. Read Cycle
Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random
read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a
command to read data of internal address register without designating an address, and is used when to verify just after
write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in
succession.
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
1st WORD
ADDRESS(n)
2nd WORD
ADDRESS(n)
SLAVE
ADDRESS
DATA(n)
SDA
LINE
WA
WAWAWAWA
A2
A1 A0
A2 A1A0
1 0 1 0
D7
D0
1
0
1 0
0
*
1312 11
14
* Don’t Care bit
R A
A
C
A
C
R
/
A
C
A
C
/
C
W K
K
K
W K
K
Figure 37. Random Read Cycle
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
DATA(n)
SDA
LINE
1 0 1 0 A2A1A0
D7
D0
A
C
K
R A
/ C
W K
Figure 38. Current Read Cycle
S
T
A
R
T
R
E
A
D
S
T
O
P
SLAVE
ADDRESS
DATA(n)
DATA(n+x)
SDA
LINE
A2 A0
A1
1
0
1
0
D7
D0
D7
D0
R A
A
C
K
A
C
K
A
C
K
/
C
W K
Figure 39. Sequential Read Cycle (in the Case of Current Read Cycle)
(1) In random read cycle, data of designated word address can be read.
(2) When the command just before current read cycle is random read cycle, current read cycle (each including
sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output.
(3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
(4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to
‘H’ while at SCL signal is ‘H’.
(5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. To end read command cycle, be sure to input 'H' to ACK
signal after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'.
(6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is
asserted from ‘L’ to ‘H’ while SCL signal is 'H'.
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TSZ22111･15･001
TSZ02201-0R2R0G100240-1-2
25.Feb.2013 Rev.002
15/30
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