Daattaasshheeeett
BM28723AMUV
Operational Notes – continued
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the LSI on the PCB. Incorrect mounting may result in
damaging the LSI. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an LSI are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the LSI. So, unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
10. Regarding the Input Pin of the LSI
This LSI contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N
junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example (refer to figure below):
When ground > Pin A and ground > Pin B, the P-N junction operates as a parasitic diode.
When ground > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the LSI. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the ground voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor( NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
N
P+
N
P+
P
P+
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
ground
P Substrate
ground
P Substrate
ground
Parasitic
Elements
Parasitic
Elements
N Region
close-by
ground
Figure 78. Example of LSI structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12. Thermal Shutdown Circuit (TSD)
This LSI has a built-in thermal shutdown circuit that prevents heat damage to the LSI. Normal operation should always
be within the LSI’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the LSI from
heat damage.
13. Over Current Protection Circuit (OCP)
This LSI incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the LSI should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
www.rohm.com
© 2018 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0C1C0E900720-1-2
31.Aug.2018 Rev.001
76/79
ROHM [ ROHM ]
