BM28723AMUV
Description of Function - continued
8
Format of Digital Audio Signal
•LRCLK: It is L/R Clock Input Signal
It is available of 32kHz/44.1kHz/48kHz with those clocks (fS) that are same to the sampling frequency (fS).
The data of the left channel and the right channel for one sample is input to this section.
•BCLK: It is Bit Clock Input Signal
It is used for the latch of data in everyone bit by sampling frequency’s 32 times frequency (32fS) or 48 times frequency
(48fS) or 64 times sampling frequency (64fS). However, if the 32fS is selected, the data length is held static of 16bit.
•SDATA: It is Data Input Signal
It is amplitude data. Word length is different according to the resolution of the input digital audio signal.
It is available of 16bit/20bit/24bit.
The digital input format is available of I2S, Left-justified and Right-justified formats.
The figure below shows the timing chart of each transmission mode.
•SDATAO: Audio Data Output After DSP Processing
This output syncs with inputted LRCLK and BCLK.
Output format is available of I2S format only.
BCLK Clock 64fS
I2S 64fs Format
LRCLK
Left Channel Right Channel
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1
BCLK
MSB
S 141312 1110 9 8
LSB
1 0
MSB LSB
S 141312 1110 9 8 7 6 5 4 3 2 1 0
SDATA
7
6 5 4 3
2
16bit Mode
20bit Mode
24bit Mode
16bit Mode
20bit Mode
24bit Mode
Left-Justified 64fs Format
LRCLK
Left Channel Right Channel
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1
BCLK
MSB
SDATA S 14 131211 10 9 8 7
LSB
0
LSB
MSB
S 14 131211 10 9 8 7 6 5 4 3 2 1 0
6
5 4 3 2
1
16bit Mode
20bit Mode
24bit Mode
16bit Mode
20bit Mode
24bit Mode
Right-Justified 64fs Format
LRCLK
Left Channel Right Channel
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1
BCLK
MSB
S 1413 1211 10 9 8
LSB
1 0
MSB LSB
S 1413 1211 10 9 8 7 6 5 4 3 2 1 0
7
6 5 4 3
2
SDATA
16bit Mode
20bit Mode
24bit Mode
16bit Mode
20bit Mode
24bit Mode
Figure 38
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TSZ02201-0C1C0E900720-1-2
31.Aug.2018 Rev.001
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