BM28723AMUV
Description of Function - continued
7
2 Wire Bus Control Signal Specification
7.1 Electrical Characteristics and Timing of Bus Line and I/O Stage
SDA
ttBBUUFF
t
t
tF
F
t
HD;STA
HD;STA
t
tLOW
tR
R
tLOW
SCL
t
tHD;DAT
t
tHIGH
tSU;DAT
tSU;STA
tSU;STO
tHD;STA
HD;STA
tSU;STA
tHIGH
tSU;DAT
tHD;STO
HD;DAT
P
S
Sr
P
Figure 32
SDA and SCL bus line characteristics(Note 18) (Unless otherwise specified Ta=25°C, VDVDD=3.3V)
High Speed Mode
Parameter
SCL Clock Frequency
Bus Free Time between a STOP and START Condition
Hold Time (repeated) START Condition.
After this period, the first clock pulse is generated.
Low Period of the SCL Clock
High Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Symbol
Unit
Min
0
1.3
Max
400
-
1
2
fSCL
tBUF
kHz
μs
3
tHD;STA
0.6
-
μs
4
5
6
7
8
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
Cb
1.3
0.6
-
-
μs
μs
μs
μs
ns
ns
ns
μs
pF
0.6
-
-
-
0(Note 17)
250
Data Set-up Time
9
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
Set-up Time for STOP Condition
20+0.1Cb
20+0.1Cb
0.6
300
300
-
10
11
12
Capacitive Load for each Bus Line
-
400
Caution: The above-mentioned numerical values are all the values corresponding to VIHmin and the VILmax level.
(Note 17) To exceed an undefined area on the fall-edge of SCL (Refer to VIH min of the SCL signal) , the transmitting set like SoC should internally offer the
holding time of 300ns or more for the SDA signal.
(Note 18) SCL and SDA pin is not corresponding to threshold tolerance of 5V.
Use it within Input voltage 1 of the absolute maximum rating.
7.2 Command Interface
2 wire Bus Control is used for command interface between host CPU. It not only writes but also it is possible to read it
excluding a part of register. In addition to Slave Address, set and write 1 byte of Select Address to read out the data. 2 wire
bus Slave mode format is illustrated below.
MSB
Slave Address
LSB
MSB
Select Address
LSB
MSB
LSB
S
A
A
Data
A
P
Figure 33
S:
Start Condition
Slave Address:
Data of 8bit in total is sent with a bit of Read mode (High) or Write mode (Low) after slave
Address (7bit) set by ADDR pin. (MSB first)
A:
Acknowledge-bit will be added byte per byte in the data that acknowledge is sent and received.
Low will be sent and received when the data is correctly sent and received.
There was no acknowledgement for High.
Select Address:
Use 1byte of select address. (MSB first)
Data:
P:
Sent and received data-byte data. (MSB first)
Stop Condition
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31.Aug.2018 Rev.001
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