DS2154
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
—
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to 1 to have RLCLK pulse at the Sa8 bit
position; set to 0 to force RLCLK low during Sa8 bit position.
See Section 14 for timing details.
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
—
RCR2.6
RCR2.5
RCR2.4
RCR2.3
RCR2.2
RCR2.1
RCR2.0
Sa7 Bit Select. Set to 1 to have RLCLK pulse at the Sa7 bit
position; set to 0 to force RLCLK low during Sa7 bit position.
See Section 14 for timing details.
Sa6 Bit Select. Set to 1 to have RLCLK pulse at the Sa6 bit
position; set to 0 to force RLCLK low during Sa6 bit position.
See Section 14 for timing details.
Sa5 Bit Select. Set to 1 to have RLCLK pulse at the Sa5 bit
position; set to 0 to force RLCLK low during Sa5 bit position.
See Section 14 for timing details.
Sa4 Bit Select. Set to 1 to have RLCLK pulse at the Sa4 bit
position; set to 0 to force RLCLK low during Sa4 bit position.
See Section 14 for timing details.
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Not Assigned. Should be set to 0 when written.
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ROCHESTER [ Rochester Electronics ]
