ADSP-BF531/ADSP-BF532/ADSP-BF533
Capacitive Loading
16
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 46). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) =
14
RISE TIME
12
2.5 V/3.3 V. Figure 47 through Figure 58 on Page 49 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out-
side the ranges shown.
10
FALL TIME
8
6
4
2
0
TESTER PIN ELECTRONICS
50Ω
V
LOAD
T1
DUT
OUTPUT
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
45Ω
70Ω
Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 1.75 V
ZO = 50Ω (impedance)
50Ω
TD = 4.04 1.18 ns
0.5pF
4pF
2pF
14
400Ω
12
RISE TIME
10
NOTES:
FALL TIME
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
8
6
4
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
2
0
Figure 46. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 2.25 V
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 3.65 V
Rev. H
| Page 47 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
