ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 36. JTAG Port Timing
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
4
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High1
System Inputs Hold After TCK High1
ns
4
4
ns
4
4
ns
5
5
ns
tTRSTW TRST Pulse Width2 (Measured in TCK Cycles)
4
4
TCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
10
12
10
12
ns
ns
tDSYS
0
0
1 System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PPI3–0.
2 50 MHz maximum
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 31. JTAG Port Timing
Rev. H
| Page 43 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
