ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Master Timing
Table 32. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tSSPIDM Data Input Valid to SCK Edge (Data Input Setup) 10.5
9
7.5
ns
ns
tHSPIDM SCK Sampling Edge to Data Input Invalid
Switching Characteristics
–1.5
–1.5
–1.5
tSDSCIM SPISELx Low to First SCK Edge
tSPICHM Serial Clock High Period
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
ns
ns
ns
ns
ns
ns
ns
ns
tSPICLM Serial Clock Low Period
tSPICLK Serial Clock Period
tHDSM Last SCK Edge to SPISELx High
tSPITDM Sequential Transfer Delay
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)
6
6
6
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold) –1.0
–1.0
–1.0
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
tHSPIDM
CPHA = 0
SPIxMISO
(INPUT)
Figure 27. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. H
| Page 39 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
