RT8876A
VCCIO
RT8876A
48
36
VCC12
12V
5V
41
VRHOT
VRHOT
35
17
VR_RDY
VCLK
VR_RDY
VCLK
VCC5
18
19
VCC5
VDIO
VDIO
43
42
V
IN
TONSET
ALERT
ALERT
TONSETA
V
IN
14
21
22
23
32
1
OFS
TEMPMAX
ICCMAX
9
RSET
DVID
13
ICCMAXA
QRSETA
2
DVIDA
QRSET
OFSA
26
20
15
IBIAS
IMON
16
V
IMONFB
CC_SENSE
10
11
COMP
FB
25
37
38
IMONA
OCSETA
OCSET
R
NTC
V
IN
52
51
50
49
BOOT1
VCC5
VCC5
UGATE1
PHASE1
LGATE1
6
5
ISEN1P
ISEN1N
R
R
NTC
NTC
40
V
IN
56
55
54
53
TSEN
VCC5
VCC5
BOOT2
UGATE2
PHASE2
LGATE2
39
24
TSENA
V
OUT_CORE
Load
3
4
ISEN2P
ISEN2N
IMONFBA
V
V
IN
CCAXG_SENSE
44
45
46
47
100
BOOT3
UGATE3
PHASE3
LGATE3
29
28
COMPA
FBA
12V
12V
7
8
ISEN3P
ISEN3N
VCC
BOOT
UGATE
12
34
PGND
RGND
EN
PHASE
LGATE
V
OUT_AXG
Chip Enable
V
SS_SENSE
33
31
PWMA
PWM
100
Load
RT9612
ISENAP
R
NTC
30
27
ISENAN
RGNDA
57 (Exposed Pad)
GND
V
SSAXG_SENSE
Figure 2. Thernal Compersation at Current Loop forAXGVR
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
22
DS8876A-02 October 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
