RT7339P
To avoid the above issue, the RT7339P provides
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Two-Layer PCB
adaptive blanking time (t ). It varies with the peak
BK
voltage of the CS pin (V
following formula :
), as shown by the
CS_PK
t
BK
= 1s + V
x 4s/V (typ.)
CS_PK
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T , listed
J(MAX)
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power
Dissipation
P
= (T T ) /
J(MAX) A JA
D(MAX)
Layout Considerations
where T
is the maximum junction temperature, T is
A
J(MAX)
A proper PCB layout can abate unknown noise
interference and EMI issue in the switching power
supply. Please refer to the guidelines when designing a
PCB layout for switching power supply :
the
ambient
temperature,
and
JA
is
the
junction-to-ambient thermal resistance.
For continuous operation, the maximum operating
junction temperature indicated under Recommended
Operating Conditions is 125C. The junction-to-ambient
The current path(1) from the input capacitor,
transformer, MOSFET, R
returning to input
capacitor is a high frequency current loop. The
path(2) from GATE pin, MOSFET, R returning to
CS
thermal resistance, , is highly package dependent. For
JA
a SOT-23-6 package, the thermal resistance, , is
JA
CS
235.6°C/W
on
a
standard
JEDEC
low
the ground of the IC is also a high frequency current
loop. They must be as short as possible to decrease
noise coupling and kept a space to other low voltage
traces, such as IC control circuit paths, especially.
Besides, the path between MOSFET ground(b) and
IC ground(d) is recommended to be as short as
possible, too.
effective-thermal-conductivity two-layer test board. The
maximum power dissipation at T = 25C can be
A
calculated as below :
P
= (125C 25C) / (235.6°C/W) = 0.42W for a
D(MAX)
SOT-23-6 package.
The maximum power dissipation depends on the
operating ambient temperature for the fixed T
and
J(MAX)
The path(3) from RCD snubber circuit to MOSFET is
the thermal resistance, . The derating curves in
JA
a high switching loop. Keep it as small as possible.
Figure 6 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
The path(4) from the input capacitor to VDD pin is a
high voltage loop. Keep a space from path(4) to
other low voltage traces.
It is good for reducing noise, output ripple and EMI
issue to separate ground traces of the input
capacitor(a), MOSFET(b), auxiliary winding(c) and
IC control circuit(d). Finally, connect them together at
the input capacitor ground(a). The areas of these
ground traces should be kept large.
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is a registered trademark of Richtek Technology Corporation.
www.richtek.com
16
DS7339P-03
August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
