RT7339P
Application Information
HV Startup Design
N
N
S
R
DMAG2
A
V
REF
= (V
+ V )
OUT
F
R
+R
DMAG1 DMAG2
The RT7339P can achieve fast startup by using the
external depletion N-MOSFET. The startup resistor RHV
is recommended to be 10k and the decoupling
capacitor is recommended to be 10F to 22F. When
VDD is designed higher than 20V, the resistor RDM
(recommended to be 1M) is required to prevent from
unstable operation at high ambient temperature.
where V is the forward voltage of the output diode.
F
V
REF
is the reference voltage of RT7339P and its
typical value is 2.5V.
COMP Response Setting
The RT7339P features the adjustable response to
improve the stability at light load. The threshold voltage
COMP Voltage Design
is set by the resistor R and the corresponding value
PC
The COMP voltage, V
follows :
, can be expressed as
COMP
can be found in the following table :
R
1.2k
3k
5.1k
PC
2
V
THDO
G
t
f
s_pk
m_ramp
V
0.4V
1.85V
2.15V
COMP_TH
on_pk
V
COMP
=
+ V
D
C
ramp
where V
is the COMP response setting
COMP_TH
where t
and f
are the peak values at V
,
IN_pk
on_pk
s_pk
threshold. When V
is lower than V
, the
COMP_TH
COMP
G
m_ramp
and C
are the fixed parameters in
ramp
RT7339P is switched to fast response.
RT7339P and the typical values are : G
=
m_ramp
Current Limit Setting
2.7A/V, C
= 6.5pF. V is the offset of the
D
ramp
constant-voltage comparator and its typical value is 2V.
is the input voltage of the THD optimizer and it
Cycle by cycle current limit is achieved by sensing the
V
THDO
voltage on the current sense resistor R . It is
CS
can be selected as different voltages by the external
Gate-to-Source resistor R . The recommended R
recommended that the maximum peak voltage of the
CS pin is designed at 80% of the current limit level.
GS
GS
is 22k or 47k, and the corresponding values of
are 1.2V and 0.9V, respectively. It is
recommended to design V = 3.5 to 4.2V. If V
Thus, R can be determined by the equation as :
CS
V
THDO
V
CL_LV
R
CS
=
80%
COMP
COMP
I
P_pk
is over 4.2V, the output voltage regulation may be
affected.
where I
is the maximum peak inductor current at
P_pk
the primary side.
Input Under-Voltage Protection Setting
Adaptive Blanking Time
The input voltage is detected by R
, which is used
DMAG1
When the MOSFET is turned off, the leakage
inductance of the transformer and parasitic capacitance
to set the input UV level (V
). Thus, R
can
DMAG1
IN_UVP
be determined by the following equation :
(C
) of the MOSFET induce resonance waveform on
OSS
N
N
P
1
A
R
= V
DMAG1
IN_pk
the DMAG pin. The resonance waveform may make
the controller false trigger the DMAG OVP, and it may
cause the controller operate in unstable condition. As
load increases, the resonance time also increases. It is
recommended to add a 10pF to 47pF bypass capacitor,
and it should be as close to DMAG pin as possible. The
larger bypass capacitor may cause phase shift on
DMAG waveform. Therefore, the output voltage
regulation will be affected.
I
DMAG_BRI
where I
is the fixed parameters in RT7339P
DMAG_BRI
and its typical value is 800A.
Output Voltage Setting
The output voltage is sensed and regulated by the
DMAG pin. When the switch is turned off, the reflected
output voltage at the auxiliary winding can be obtained
and expressed as follows :
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS7339P-03
August 2019
www.richtek.com
15
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
