RT7262E
Layout Considerations
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the IC.
Follow the PCB layout guidelines for optimal performance
of the IC.
` Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
` Keep the traces of the main current paths as short and
wide as possible.
` Put the input capacitor as close as possible to the device
` An example of PCB layout guide is shown in Figure 8
pins (VINandGND).
for reference.
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pickup.
Place the input and output
capacitors as close to the
IC as possible.
GND
CIN
SW should be
connected to
14
VIN
SW
SW
SW
SW
1
2
3
4
5
6
7
AGND
GND
GND
VCC
SS
PGOOD
13
12
11
10
9
CSS
inductor by wide
and short trace and
keep sensitive
components away
from this trace.
GND
CBOOT
Place the
R2
R1
BOOT
EN/SYNC
feedback as
close to the IC
as possible.
15
8
FB
RT
L
VOUT
GND
VOUT
COUT
Figure 8 (a). PCB Layout Guide for WDFN-14L 4x3
Place the input and
output capacitors
as close to the IC
as possible.
GND
CIN
SW should be connected
8
7
6
5
VIN
SW
GND
VCC
FB
to inductor by wide and
short trace and keep
sensitive components
away from this trace.
2
3
4
R2
R1
Place the feedback
as close to the IC as
possible.
RT
GND
SW
9
BOOT
EN/SYNC
CBOOT
L
VOUT
COUT
VOUT
GND
Figure 8 (b). PCB Layout Guide for SOP-8 (Exposed Pad)
Copyright 2012 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
©
DS7262E-00 November 2012
www.richtek.com
15
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
