RT7262E
EN
R
Operating Frequency and Synchronization
EN
The internal oscillator runs at 500kHz (typ.) when the EN/
SYNC pin is at logic-high level (>2V). If the EN pin is
pulled to low-level for 10μs above, the IC will shut down.
The RT7262E can be synchronized with an external clock
ranging from 300kHz to 2MHz applied to the EN/SYNC
pin. The external clock duty cycle must be from 30% to
90%.
V
EN
RT7262E
IN
C
EN
GND
Figure 3. Enable Timing Control
An external MOSFET can be added to implement digital
control on the EN pin, as shown in Figure 4. In this case,
a 100kΩ pull-up resistor, REN, is connected between VIN
pin and the ENpin. MOSFET Q1 will be under logic control
to pull down the EN pin.
10µs
2ms
VIN
EN/SYNC
VCC
R
EN
VOUT
100k
V
EN
RT7262E
GND
IN
Q1
EN
CLK
External CLK
Figure 6. Startup Sequence Using External Sync Clock
Figure 6 shows the synchronization operation in startup
period. When the EN/SYNC is triggered by an external
clock, the RT7262E enters soft-start phase and the output
voltage starts to rise. During the soft-start phase region,
the oscillation frequency will be proportional to the feedback
voltage until it is higher than 0.7V. With higher VFB, the
switching frequency is relatively higher. After startup period
about 2ms, the IC operates with the same frequency as
the external clock.
Figure 4. Digital Enable Control Circuit
The chip starts to operate when VIN rises to 4.2V (UVLO
threshold). During the VIN rising period, if an 8V output
voltage is set, VIN is lower than the VOUT target value and
it may cause the chip to shut down. To prevent this
situation, a resistive voltage divider can be placed between
the input voltage and ground and connected to the ENpin
to adjust enable threshold, as shown in Figure 5. For
example, the setting VOUT is 8V and VIN is from 0V to
12V, when VIN is higher than 10V, the chip is triggered to
enable the converter. Assume REN1 = 50kΩ. Then,
Power Good Output
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is lower than
70% of its set voltage, PGOOD will be pulled low. It is
held low until the output voltage returns to within the allowed
tolerances once more.During soft-start, PGOODis actively
held low and only allowed to transition high after soft-start
is over and the output voltage has reached 90% of its set
voltage.
(R
(V
x V
)
)
EN1
IH(MIN)
R
EN2
=
− V
IN_S
IH(MIN)
where VIH(MIN) is the minimum threshold of enable rising
(2V) and VIN_S is the target turn on input voltage (10V in
this example). According to the equation, the suggested
resistor R EN2 is 12.5kΩ.
R
EN1
V
IN
EN
Under Output Voltage Protection-Hiccup Mode
R
EN2
RT7262E
GND
For the IC, Hiccup Mode of Under Voltage Protection (UVP)
is provided. When the FB voltage drops below half of the
feedback reference voltage, VFB, the UVP function will be
triggered and the IC will shut down for a period of time and
Figure 5. ResistorDivider for Lockout Threshold Setting
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DS7262E-00 November 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
