RT7262E
The selection of COUT is determined by the required ESR
to minimize voltage ripple.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WDFN-14L 4x3 package, the thermal resistance, θJA, is
30°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For SOP-8 (Exposed Pad) package, the thermal
resistance, θJA, is 61.2°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
Moreover, the amount of bulk capacitance is also a key
for COUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response.
The output ripple, ΔVOUT, is determined by :
1
⎡
⎤
ΔVOUT ≤ ΔIL ESR +
⎢
⎣
⎥
⎦
8fCOUT
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
PD(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for
WDFN-14L 4x3 package
PD(MAX) = (125°C − 25°C) / (61.2°C/W) = 1.63W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.6
Four-Layer PCB
WDFN-14L 4x3
3.0
Thermal Shutdown
2.4
Thermal shutdown is implemented to prevent the chip from
operating at excessively high temperatures. When the
junction temperature is higher than 150°C, the chip is
shut down the switching operation. The chip is
automatically re-enabled when the junction temperature
cools down by approximately 30°C.
SOP-8 (Exposed Pad)
1.8
1.2
0.6
0.0
0
25
50
75
100
125
Thermal Considerations
Ambient Temperature (°C)
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Figure 7. Derating Curve of Maximum PowerDissipation
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
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is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DS7262E-00 November 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
