RT6255A/B
Layout Considerations
2.5
2.0
1.5
1.0
0.5
0.0
Four-Layer PCB
Follow the PCB layout guidelines for optimal performance
of the device.
Keep the traces of the main current paths as short and
wide as possible.
TSOT-23-6 (FC)
TSOT-23-8 (FC)
Put the input capacitor as close as possible to VIN pin.
LX node is with high frequency voltage swing and should
be kept at small area. Keep analog components away
from the LX node to prevent stray capacitive noise pickup.
Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the device.
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum PowerDissipation
Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
TheAGNDpin is suggested to connect to 2nd GNDplate
through top to 2nd via.
An example of RT6255A/B PCB layout guide is shown
in Figure 8 and Figure 9 for references.
The feedback components must be
connected as close to the device as possible.
V
OUT
C
Keep sensitive components away
from this trace. Suggestion layout
trace wider for thermal.
OUT
The R component must
EN
V
OUT
be connected to V
.
IN
C
OUT
Suggestion layout trace
wider for thermal.
R1
R2
FB
EN
6
5
4
BOOT
LX should be connected to inductor by
Wide and short trace. Keep sensitive
components away from this trace.
L
C
R
B
EN
V
2
3
IN
LX
Suggestion layout trace wider for thermal.
GND
VIN
Suggestion layout trace
wider for thermal.
Input capacitor must be placed as close
to the IC as possible. Suggestion layout
trace wider for thermal.
C
C
IN
IN
Figure 8. PCB LayoutGuide for TSOT-23-6 package
Copyright 2017 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6255A/B-02 March 2017
www.richtek.com
17
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