RT6243A/B
which is proportional to the switch current, during the on-
time of LSFET. To improve the current measurement
accuracy, temperature compensation is added internally.
If the measured drain to source voltage of the LSFET is
above the voltage proportional to current limit, the LSFET
stays on until the current level becomes lower than the
OCL level which reduces the output current available.
When the current is limited the output voltage tends to
drop because the load demand is higher than what the
converter can support.
When the output voltage falls below Output UVP Threshold
(V
UVP
), the UVP comparator detects it and shuts down
the device to avoid the excessive heat. If the UVP condition
remains for a period of time, a soft-start sequence for
auto-recovery will be initiated. It is shown in Figure 4.
When the overcurrent condition is removed, the output
voltage returns to the regulated value.
V
OUT
, 1V/Div
Fault condition removed
Resume normal operation
Output Short
a pull-up resistor. The power-good function is activated
after soft-start is finished and is controlled by the feedback
signal V
FB
. During soft-start, PGOOD is actively held low
and only allowed to transition high after soft-start is over.
If V
FB
rises above a power-good threshold V
TH_PGLH
(typically 93% of the target value), the PGOOD pin will be
in high impedance and V
PGOOD
will be held high after a
certain delay elapsed. When V
FB
drops by a V
FB
falling
hysteresis
ΔV
TH_PGLH
(typically 9% of the target value) or
exceeds V
FB
rising threshold V
TH_PGHL
typically 116% of
the target value), the PGOOD pin will be pulled low. For
V
FB
above V
FB
falling hysteresis, V
PGOOD
will be pulled
high again when V
FB
drops back by a power-good
hysteresis
ΔV
TH_PGHL
(typically 9% of the target value).
Once being started-up, if any protection is triggered (UVP
and OTP) or EN is from high to low, PGOOD will be pulled
to GND. The internal open-drain pull down device with
250Ω resistance will pull the PGOOD pin low. To prevent
unwanted PGOOD glitches during transients or dynamic
VOUT changes, the RT6243A/B's PGOOD falling edge
includes a blanking delay of approximately 1μs.
V
TH_PGHL
VTH_PGHL
VTH_PGHL
I
L
, 10A/Div
V
PGOOD,
4V/Div
V
SW
, 10V/Div
V
TH_PGLH
VTH_PGLH
VTH_PGLH
V
FB
50ms/Div
V
PGOOD
Figure 4. Current Limit and UVP
Similar to the forward overcurrent, the reverse current
protection is realized by monitoring the current across
the low-side MOSFET. When the LSFET current reaches
negative current limit, the synchronous rectifier is turned
off. This limits the ability of the regulator to actively pull-
down on the output.
Note. In order to prevent the NOC is triggered on light
load operation, the inductor valley current should be
designed to higher than I
LIM_NEG
when the MODE selection
is FCCM.
Power-Good Output
The PGOOD pin is an open-drain power-good indication
which is connected to an external voltage source through
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
Figure 5. The Logic of PGOOD
Output Over-Voltage Protection (OVP)
The RT6243A/B provides an over-voltage protection (OVP),
If the FB voltage (V
FB
) rises above 121% of the internal
reference voltage, the over-voltage protection is triggered,
the discharging switch from SW to GND is turned on to
discharge output voltage.
Over-Temperature Protection (OTP)
The RT6243A/B monitors the internal die temperature. If
this temperature exceeds the thermal shutdown threshold
value (T
SD
, typically 160°C), the RT6243A/B stops
switching with SS reset to ground and an internal discharge
switch turns on to quickly discharge the output voltage.
During start up, if the device temperature is higher than
is a registered trademark of Richtek Technology Corporation.
DS6243A/B-01 June 2019
www.richtek.com
7
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
