RT6243A/B
Once both of the external and internal soft-start ramps
have exceeded
0.7V, the output voltage will be in
regulation. The typical external soft start time can be
calculated by the equation below.
C
SS
nF
=
t
SS
ms
I
SS
μA
V
REF
V
Pre-Bias
If there is a residual voltage on output voltage before start-
up, both of the internal HSFET and LSFET are prohibited
switching until the soft start ramp is higher than feedback
voltage. When the soft start ramp cross above the feedback
voltage, switching will begin and the output voltage will
smoothly rise from the pre-biased level to its regulated
target.
Mode Selection for Light Load Operation,
Switching Frequency and Current Limit
0.7V
Where I
SS
= 6μA, V
REF
= 0.6V
When the V
EN
is lower than V
ENL
, the SS pin voltage is
reset to GND.
VCC
I
SS
SS
C
SS
V
SS
V
FB
t
SS
0.1V
MODE pin offers 12 different states of operation as a
combination of Light Load operation, Switching Frequency
and Current Limit. As shown in the Figure 3, use a resistor
divider from VCC to AGND can set the MODE pin voltage.
It is important that the voltage for the MODE pin is derived
from the VCC rail only since internally this voltage is
referenced to detect the MODE option. The device reads
the voltage on the MODE pin during start-up and latches
onto one of the MODE options listed below in Table 1.
The MODE pin setting can be reset only by a VIN power
cycling. The two resistors (R
M1
and R
M2
) are suggested to
use 1% resistors.
VCC
RT6243A/B
MODE
PGND
AGND
R
M2
C
VCC
Figure 1. External Soft-Start Time Setting
Figure 2 below shows the typical power-up sequence of
the device when the EN pin voltage crosses the EN Input
rising threshold. After the voltage on VCC pin crosses the
UVLO rising threshold it takes 400μs to read the first
MODE setting and approximately 55μs from there to finish
the last MODE setting. The output voltage starts ramping
after the MODE setting reading is completed.
R
M1
V
IN
Figure 3. MODE Connection
V
ENH
V
EN
V
UVLOH
V
CC
When the V
MODE
< Internal
DAC, the Mode is latched.
Mode12
V
MODE
Internal DAC
Mode1
V
OUT
400µs
55µs
t
SS
(1.045ms)
Figure 2. Power Up Sequence
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS6243A/B-01 June 2019
www.richtek.com
5
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
