RT6243A/B
Operation
The RT6243A/B is a high efficiency synchronous step-
down converter utilizes the proprietary Advanced Constant
On-Time (ACOT
TM
) control architecture. The ultrafast
ACOT
TM
control enables the use of small capacitance to
save the PCB size.
During normal
operation, the internal high-side power
switch (HSFET) turns on for a fixed interval determined
by a one-shot timer at the beginning of each clock cycle.
When the HSFET turns off, the low-side power switch
(LSFET) turns on. Due to the output capacitor ESR, the
voltage ripple on the output has similar shape as the
inductor current. Via the feedback resistor network, this
voltage ripple compared with the internal reference. When
the minimum off-time one-shot (310ns, max.) has timed
out and the inductor current is below the current limit
threshold, the One-shot is triggered again if
the feedback
voltage falls below the feedback reference voltage (0.6V,
typ.). To achieve stable operation with low-ESR ceramic
output capacitors, an internal ramp signal is added to the
feedback reference voltage to simulate the output voltage
ripple. ACOT
TM
control architecture features ultrafast
transient response. When a load is suddenly increased,
the output voltage drops quickly, and almost immediately,
a new On-time is triggered, and inductor current rises
again.
Traditional COT controller implements the on-time to be
inversely proportional to input voltage and directly
proportional to the output voltage to achieve pseudo-fixed
frequency over the input voltage range. But even with
defined input and output voltages, a fixed ON time will
mean that frequency will have to increase at higher load
levels to compensate for the power losses in the MOSFETs
and Inductor. ACOT control further added a frequency
locked loop system, which slowly adjusts the ON time to
compensate the power losses, without influencing the fast
transient behavior of the COT topology.
Power and Bias Supply
The VIN pins on the RT6243A/B are used to supply voltage
to the drain terminal of the internal
HSFET. These pins
also supply bias voltage for an internal regulator that
generates 4.7V at VCC. The voltage on VCC pin is used
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
TM
for internal chip bias and gate drive for the LSFET. The
gate drive for the HSFET is supplied by a floating supply
(C
BOOT
) between the BOOT and SW pins, which is charged
by an internal synchronous diode from VCC. In addition,
an internal charge pump maintains the C
BOOT
voltage is
sufficient to turn-on the HSFET.
To improve efficiency and limit power dissipation in the
VIN, an external voltage that is above the LDO's internal
output voltage can override the internal LDO. When using
an external bias on the VCC rail, any power-up and power-
down sequencing can be applied but it is important to
understand that if there is a discharge path on the VCC
rail that can pull a current higher than the internal LDO's
current limit from the VCC, then the VCC drops below the
UVLO falling threshold and thereby shutting down the
output of the RT6243A/B.
Enable, Start-Up, Shutdown and UVLO
The RT6243A/B implements Under-Voltage Lock Out
protection (UVLO) to prevent operation without fully turn-
on the internal power MOSFETs. The UVLO monitors the
internal VCC regulator voltage. When the VCC voltage is
lower than UVLO threshold voltage, the device stops
switching. UVLO is non-latching protection.
The EN pin is provided to control the device turn-on and
turn-off. When EN pin voltage is above the turn-on
threshold (V
ENH
), the device starts switching and when
the EN pin voltage falls below the turn-off threshold (V
ENL
)
it stops switching. The EN pin of the RT6243A has internally
pull-up with current source. However, the RT6243B
internally week pull-down the EN pin.
When appropriate voltages are present on the VIN, VCC,
and EN pins, the RT6243A/B will begin switching and
initiate a soft-start ramp of the output voltage. An internal
soft-start ramp of 1.045ms will limit the ramp rate of the
output voltage to prevent excessive input current during
start-up. If a longer ramp time is desired, a capacitor can
be placed from the SS pin to ground. The 6μA current that
is sourced from the SS pin will create a smooth voltage
ramp on the capacitor. If this external ramp rate is slower
than the internal 1.045ms soft-start, the output voltage
will be
limited by the ramp rate on the SS pin instead.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS6243A/B-01 June 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
