RT3602AP
Operation
The RT3602AP adopts G-NAVP
TM
(Green Native AVP)
which is Richtek's proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning).
The G-NAVP
TM
Current Balance
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
Offset Cancellation
Cancel the current/voltage ripple issue to get the accurate
VSEN.
UVLO
Detect the VCC voltage and issue POR signal as they
are high enough.
DAC
controller is one type of current mode
constant on-time control with DC offset cancellation. The
approach can not only improve DC offset problem for
increasing system accuracy but also provide fast transient
response. When current feedback signal reaches COMP
signal, the RT3602AP generates an on-time width to
achieve PWM modulation.
TON GEN/Driver Interface PWMx
Generate the PWMx sequentially according to the phase
control signal from the Loop Control/Protection Logic.
Pulse width is determined by current balance result and
pin setting. Once quick response mechanism is triggered,
VR allows all PWM to turn on at the same time. PWM
status is also controlled by Protection Logic. Different
protections may cause different PWM status (Both High-
Z or LG turn-on).
SVID Interface/Configuration Registers/Control
Logic
The interface receives the SVID signal from CPU and sends
the relative signals to Loop Control/Protection Logic for
loop control to execute the action by CPU. The registers
save the pin setting data from ADC output. The Control
Logic controls the ADC timing, generates the digital code
of the VID for VSEN voltage.
Loop Control/Protection Logic
It controls the power on sequence, the protection behavior,
and the operational phase number.
MUX and ADC
The MUX supports the inputs from SET1, SET2, SET3,
IMON_MAIN, IMON_AUXI, TSEN_MAIN and TSEN_AUXI.
The ADC converts these analog signals to digital codes
for reporting or performance adjustment.
Generate an analog signal according to the digital code
generated by Control Logic.
Soft-Start & Slew Rate Control
Control the Dynamic VID slew rate of VSEN according to
the SetVID fast or SetVID slow.
Error Amp
Error amplifier generates COMP_MAIN/COMP_AUXI/
COMP_SA signal by the difference between output of
MAIN/AUXI/SA rail and FB_MAIN/FB_AUXI/FB_SA.
PWM CMP
The PWM comparator compares COMP signal and current
feedback signal to generate a signal for TON trigger.
IMON Filter
IMON Filter is used for average sum current signal by
analog RC filter.
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS3602AP-00
September 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
