RT3602AP
Functional Block Diagram
VSEN_MAIN
TSEN_MAIN
VSEN_AUXI
TSEN_AUXI
VR_READY
VR_HOT
ALERT
PSYS
VCLK
SET1
SET2
SET3
VDIO
MUX
IMONI_SA
ADC
IMONI_MAIN
ADC
IMONI_AUXI
ADC
ADC
SVID Interface
Configuration Registers
Control Logic
QRTH
QRWIDTH
OCS
AI
TONSET
IMAX
ADDR
OLL
ANTIOVS
OCP
PWM
CMP
QR
QRWIDTH
TONSET
RAMP
+
IMONI_AUXI
From Control Logic
RGND_MAIN
DAC
Soft-Start &
Slew Rate Control
VSET_MAIN
ERROR
AMP
+
-
IB1
+
-
+
-
IMONI_MAIN
+
OCS/OCP_TH
From Control Logic
RGND_SA
DAC
Soft-Start &
Slew Rate Control
VSET
ERROR
AMP
+
-
PWM
CMP
QR
QRWIDTH
TONSET
RAMP
+
IMONI_SA
OCS/OCP_TH
-
ISENN
OC
To Protection Logic
OV/UV/NV
-
ISEN1N_MAIN
OV/UV/NV
x100% x100%
IB1
IB2
OC
To Protection Logic
Current
Balance
IB2
RAMP
AI
PWM
CMP
QR
QRWIDTH
TONSET
OCS/OCP_TH
-
ISEN1N
OC
To Protection Logic
VINR
OV/UV/NV
VIN
Loop Control Protection
Logic
UVLO
GND
VCC
EN
DRVEN
From Control Logic
RGND_AUXI
DAC
Soft-Start &
Slew Rate Control
VSET_AUXI
ERROR
AMP
+
-
FB_AUXI
COMP_AUXI
AI
ISENP_AUXI
ISENN_AUXI
IMON_AUXI
+
-
Offset
Cancellation
+
+
-
TON
GEN/
Driver
Interface
PWM_AUXI
FB_MAIN
COMP_MAIN
ISEN1P_MAIN
ISEN1N_MAIN
VREF
ISEN2P_MAIN
ISEN2N_MAIN
IMON_MAIN
+
-
Offset
Cancellation
Current Mirror
+
+
-
TON
GEN/
Driver
Interface
PWM1_MAIN
PWM2_MAIN
FB_SA
COMP_SA
AI
ISENP_SA
ISENN_SA
IMON_SA
+
-
Offset
Cancellation
+
+
-
TON
GEN/
Driver
Interface
PWM_SA
Copyright
©
2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS3602AP-00
September 2019
www.richtek.com
5
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
