Proposed
RF2722
Receiver Configuration Register 1 (CRX1) - Address 100000
Location
Bit Name Default
Description
CRX1(11)
reserved
LO_PH_CAL
CLK BYP
0
0000
1
Reserved
CRX1(10:7)
CRX1(6)
I/Q Phase Calibration
If set to zero, then the CLK_IN pin is AC-coupled. If set to one, then the CLK_IN pin is
DC-coupled.
CRX1(5)
CLKF
0
Input clock frequency select. (Must be set to 26MHz for normal
operation.) Programming this bit high activates a divide-by-two function on the
CLK_IN pin. Programming this bit low deactivates the divide-by-two function. The
DC offset correction circuitry requires a 26MHz clock for proper operation. There-
fore, CLKF should be programmed low if a 26MHz clock is provided to the
CLK_IN pin.
0=CLK_IN frequency is 26MHz
1=CLK_IN frequency is 52MHz
CRX1(4)
CRX1(3)
CRX1(2)
CRX1(1:0)
VCOSEL
VCOEN
TXSEL
TEST
0
0
When set to zero, the VCO is turned on and off by RX_EN. When programmed high,
the VCO is controlled by the VCOEN bit instead of RX_EN.
When VCOSEL is set to one, then VCOEN turns on and off the VCO. When VCOEN is
set to zero, the VCO is off. When VCOEN is set to one, the VCO is turned on.
1
If programmed high, the TX buffers are enabled by the TX_EN pin. If programmed
low, the TX buffers are enabled by CF[16].
00
Test Output Selection Bits: The GPO1 pin provides test signal outputs as well as
the activation signal for the RF6001 RX system. The available signals are
shown below.
00
01
10
11
Normal output of GPO1 pin
Serial data shifting through Configuration Registers
MSB bit of the VCO calibration counter
dcadapt counter 2 output
Receiver Configuration Register 2 (CRX2) - Address 100001
Programming Bits
# of Bits
Default
Description
CRX2(11)
DC_ST
0
If programmed high, the DC correction system is activated when the SDI word is
loaded. DC_ST will revert low once the DC correction system is activated. RX EN
needs to be high for DC_ST to operate correctly.
CRX2(10)
CRX2(9)
CRX2(8)
DC_EN
LND
1
0
0
If programmed high, the DC correction system is activated on the rising edge of
RX_EN (default=1).
If programmed high, the LNA’s are disabled during the time interval of the DC correc-
tion system.
TRD
If programmed high, GPO1 and GPO2 follow TRDC instead of the normal GP0 pro-
gramming during the time interval defined by DC_TIME2.
CRX2(7)
CRX2(6)
TRTX_EN
reserved
TRDC
0
0
If programmed high, the functionality defined by TRTXA is active.
Reserved
CRX2(5:4)
00
If TRD is set true, then during the time interval defined by DC_TIME2, GPO1
and GPO2 are reassigned as follows.
GPO1=TRDC[0]
GPO2=TRDC[1]
CRX2(3:2)
CRX2(1:0)
TRTXA
GPO
00
00
If TRTX_EN is programmed high, while TXEN pin is high the GPO outputs are
reassigned as follows:
GPO1=TRTXA[0]
GPO2=TRTXA[1]
The states of each bit within this word are transferred to the corresponding GP0 pin
as follows.
GPO1=GPO[0]
GPO2=GPO[1]
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Rev A4 DS050919
21 of 26
RFMD [ RF MICRO DEVICES ]
