ML5805
RECOMMENDED CONFIGURATION REGISTER VALUES
Data Rate (kbps)
Register
576
1152
1536
1755
2048
R0
R1
R2
R3
R4
0x017A
0xF482
0xC000
0x0080
0x3600
0x057A
0xF482
0xC000
0x0080
0x4800
0x097A
0xC482
0xC000
0x0080
0x5D00
0x0D7A
0x8482
0xC000
0x0080
0x6400
0x117A
0x8482
0xC000
0x0080
0x5200
Table 6 Recommended register values for each data rate
Please consult with RFMD application engineering for updates to these values or if you have special
configuration requirements. The recommended register settings in Table 6 initialize the ML5805 as follows;
DOUT enabled (AOUT disabled),
force 300μs data slicer time constant,
CDR disabled,
RSSI muting while PLL is not locked,
3.44V PA regulator,
minimum RX to TX delay,
minimum PA on to T/R switch delay and,
minimum PA off to T/R switch delay.
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APRIL 2008
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