ML5805
REGISTER 1
Bit
Variable
Default
Definition
CDRDLY
15:12
8
Recovered Data Clock Delay (RDCdelay) is the delay between the
rising edge of RX data and the rising edge of the recovered RX data
clock. The CDRDLYvariable sets this delay as follows;
RDCdelay = CDRDLY/ ( 2 x f ref ) [default RDCdelay = 325 ns]
CDREN
11
0
0
1: enable RDCdelay
0: RDCdelay is not used
Current Setting for PA.
Value Definition
TXPADRV
10:8
0
1
2
3
4
5
6
7
Bias current setting = 63uA
Bias current setting = 280uA
Bias current setting = 368uA
Bias current setting = 605uA
Bias current setting = 605uA
Bias current setting = 822uA
Bias current setting = 930uA
Bias current setting = 1177uA
RSSIDLY
7
1
0
0
0
0
0
0
1: RSSI output is masked until the PLL finished tuning
0: RSSI will function during the PLL tuning change time
1: the PA turns on before the external switch controls change
0: the external switch controls change before the PA is turned on
1: clock TX data on the falling edge of the reference clock
0: clock TX data on the rising edge of the reference clock
1: invert the TX data before filtering
PAFIRST
6
TXFILTEDGE
TXFILTPOL
NOIVCOC
5
4
0: no data inversion applied
3
1: no incremental VCO calibration, only incremental IF calibration
0: perform both VCO and IF incremental calibrations
1: one error is allowed for the DECT unique word detection
0: zero errors are allowed for the DECT unique word detection
IF and PA Circuit Regulator Voltages
UW1ERR
2
IFREGSEL
1:0
Value Definition
0
1
2
3
Regulator output = 3.3V
Not valid
Regulator output = 3.44V
Regulator output = 3.67V
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PRELIMINARY DATA SHEET
APRIL 2008
EDS-106041 REV P01
7628 THORNDIKE ROAD, GREENSBORO, NC 27409-9421 · FOR SALES OR TECHNICAL
REV A1 DS071026 SUPPORT, CONTACT RFMD AT (+1) 336-678-5570 OR SALES-SUPPORT@RFMD.COM
24
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