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ML5805DM-T 参数 Datasheet PDF下载

ML5805DM-T图片预览
型号: ML5805DM-T
PDF下载: 下载PDF文件 查看货源
内容描述: 5.8GHz的可变数据速率FSK收发器,集成PA [5.8GHz Variable Data Rate FSK Transceiver with Integrated PA]
分类和应用:
文件页数/大小: 36 页 / 1698 K
品牌: RFMD [ RF MICRO DEVICES ]
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ML5805  
SERIAL BUS CONTROL: EN, DATA, CLK  
A 3-wire serial interface is used for programming the ML5805 configuration registers, which control device mode of  
operation, pin functions, PLL and reference dividers, internal test modes and filter alignment. Data words are entered  
beginning with the MSB. The 24 bit configuration register word consists of 5 bit address and 16 bit data fields.. When  
the address field has been decoded the destination register is loaded on the rising edge of EN. Note: Providing less  
than 24 bits of data will result in unpredictable behavior when EN goes high.  
Data and clock signals are ignored when EN is high. When EN is low, data on the DATA pin is clocked into a shift  
register by rising edges on the CLK pin. The information is loaded into the addressed latch when EN returns high. This  
serial interface bus is an industry standard bus commonly found on PLL devices. It can be efficiently programmed by  
either byte or 24-bit word oriented serial bus hardware. The data latches are implemented in CMOS and use minimal  
power when the bus is inactive (see Figure 5 and Table 3).  
tf  
ts  
tck  
th  
tr  
tl  
CLK  
Data  
tse  
MSB  
tew  
EN  
Figure 5: Serial Bus Timing Diagram  
SYMBOL PARAMETER  
BUS CLOCK (CLK)  
MIN MAX UNITS  
Clock input rise time (Note 1)  
tr  
15  
15  
ns  
ns  
ns  
Clock input fall time (Note 1)  
Clock period  
tf  
tck  
50  
ENABLE (EN)  
tew  
tl  
Minimum pulse width  
200  
15  
ns  
ns  
ns  
Delay from last clock rising edge to rise of EN  
Enable set up time to ignore next rising clock  
tse  
15  
BUS DATA (DATA)  
ts  
Data to clock set up time  
Data to clock hold time  
15  
15  
ns  
ns  
th  
Table 3: Serial Bus Timing Specifications  
Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times can  
be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and all set up  
and hold time minimums are met with respect to the CMOS switching points (VIL MAX and VIH MIN). The serial I/O clock rise  
and fall times are limited to an absolute maximum of 100ns.  
RF MICRO DEVICES®, RFMD®, OPTIMUM TECHNOLOGY MATCHING®, ENABLING WIRELESS CONNECTIVITY™, POWERSTAR®, POLARIS™ TOTAL RADIO™ ULTIMATEBLUE™ AND FASTWAVE™ ARE TRADEMARKS OF RFMD, LLC. BLUETOOTH IS A TRADEMARK OWNED BY  
BLUETOOTH SIG, INC., U.S.A. AND LICENSED FOR USE BY RFMD. ALL OTHER TRADE NAMES, TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ©2006, RF MICRO DEVICES, INC.  
PRELIMINARY DATA SHEET  
APRIL 2008  
EDS-106041 REV P01  
7628 THORNDIKE ROAD, GREENSBORO, NC 27409-9421 · FOR SALES OR TECHNICAL  
REV A1 DS071026 SUPPORT, CONTACT RFMD AT (+1) 336-678-5570 OR SALES-SUPPORT@RFMD.COM  
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