ML5805
Table 2 shows the minimum time required between control interface transitions.
SYMBOL
PARAMETER
WORST
CASE
UNITS
TIMING
tWAKE
tFH
Time from XCEN asserted to valid RECEIVE data out
325
110
μsec
μsec
Time from rising edge of Serial Bus EN to valid RECEIVE data out (channel
scan mode, one channel hop, PLL re-locking triggered by rising EN).
NOIVCOC= 0
55
90
80
70
NOIVCOC= 1
NOIVCOC= 0
NOIVCOC= 1
tTX2RX
Time from rising edge of RXON to valid RECEIVE data out
μsec
μsec
tRX2TX
tTXONA
Time from falling edge on RXON to start of valid data on DIN pin. Some RF energy will be present on TXO
during this period but PAON will be unasserted
For the case where PAFIRST = 0: tTXONA defines the time between falling edge of RXON and rising edge of
RF output power
For the case where PAFIRST = 1: tTXONA defines the time between falling edge of RXON and rising edge of
SW_CTRL_P
tTXONA = 44μS + TTXONA* 8 / f ref where TTXONAis an integer with range from 0 to 63
44 to 85
μsec
tTXONB
For the case where PAFIRST = 0: tTXONB defines the time between rising edge of SW_CTRL_P and rising
edge of RF output power
For the case where PAFIRST = 1: tTXONB defines the time between rising edge of RF output power and rising
edge of SW_CTRL_P
tTXONB = 4.2μS + TTXONB* 8 / f ref where TTXONBis an integer with range from 0 to 31
4.2 to 24.2
3.5 to 13.5
μsec
μsec
tTXOFF
Time between falling edge of RF output power and falling edge of SW_CTRL_P signal
t
TXOFF = 3.5μS + TTXOFF* 40 / f ref where TTXOFFis an integer with range from 0 to 3
Table 2: Transceiver Control Interface Timing (using default register values)
Channel Scan Timing in Receive Mode
To implement channel scanning, the ML5805 is kept in RECEIVE mode (XCEN and RXON high) and the PLL is
reprogrammed to select a different RF channel. A VCO and filter calibration cycle is initiated periodically after the serial
bus writes to the register controlling the PLL. Any serial bus writes to the other registers (while XCEN = VIL (0)) will
trigger a complete calibration cycle. Non-PLL register writes (R0 to R4) are only performed when XCEN = VIL (0).
Otherwise, unstable operation will occur. Signal diagram for channel scanning is shown in Figure 3.
XCEN
tWAKE
tFH
EN (Write to PLL
tuning register)
DOUT
Valid RX Data
Valid RX Data
Figure 3: Control Timing when Channel Scanning
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PRELIMINARY DATA SHEET
APRIL 2008
EDS-106041 REV P01
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