ML5805
STANDBY MODE
In STANDBY mode, the ML5805 transceiver is powered down. The only active circuits are the control interfaces, which
are static CMOS to minimize power consumption. The serial control interface and control registers remain powered up
and will accept and retain programming data as long as the VDD and VCCA are present.
RECEIVE MODE
In RECEIVE mode, the received signal at 5.8GHz is down converted, band pass filtered (IF filter), fed to the frequency-
to-voltage converter, and then low-pass filtered. The output of the low-pass filter is available at both the AOUT pin and
to the on-chip data slicer that produces NRZ digital data presented at the DOUT pin. An RSSI output voltage is also
provided.
TRANSMIT MODE
In TRANSMIT mode, the PLL loop is closed to eliminate frequency drift. A closed loop FSK modulator modulates both
the VCO and the fractional-N PLL. The VCO is directly modulated with filtered FSK transmit data. The PLL is driven by
a sigma-delta modulator, which ensures that the PLL follows the mean frequency of the modulated VCO.
CONTROL INTERFACE
There are two types of Input/output (I/O) signals to control and monitor the ML5805; Discrete I/O and Serial input.
Discrete I/O:
XCEN, RXON, SW_CTRL_P, SW_CTRL _N, DATASEL
Serial Control Bus: EN, DATA, CLK
The ML5805 transceiver is used in time division duplex (TDD) mode, where the transceivers at each end of a radio link
alternately transmit and receive. Prior to entering receive mode, the ML5805 goes through a ‘self-calibration’ sequence,
where the VCO, IF and data filters are frequency aligned. This occurs in the time period just before the PLL settles to
the LO frequency. These calibration cycles are triggered by logic transitions on the control interface. Figure 2a and 2b
show the normal operating cycle for the ML5805. Figure 2a shows the timing when register variable PAFIRSTis set to
0, causing the switch control signals to change state before the PA is enabled. Figure 2b shows the timing when register
variable PAFIRSTis set to 1, causing the switch control signals to change state after the PA is enabled.
RF CONTROL: XCEN, RXON, SW_CTRL
The XCEN pin enables/disables the ML5805 and places the device in either STANDBY or ACTIVE modes.
The RXON pin determines which active mode the ML5805 is in: RECEIVE or TRANSMIT.
SW_CTRL_P and SW_CTRL_N are complimentary CMOS outputs with 5mA drive capability that control an off-chip
T/R switch. They can directly drive PIN diodes. SW_CTRL_P outputs a logic high when RXON is asserted low and a
logic low at all other times. The time delays between RXON and SW_CTRL_P are programmable are shown in Figure 2
and Table 3. These outputs are inhibited when the PLL is not locked.
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PRELIMINARY DATA SHEET
APRIL 2008
EDS-106041 REV P01
7628 THORNDIKE ROAD, GREENSBORO, NC 27409-9421 · FOR SALES OR TECHNICAL
REV A1 DS071026 SUPPORT, CONTACT RFMD AT (+1) 336-678-5570 OR SALES-SUPPORT@RFMD.COM
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