ML5805
16
VTUNE
I (analog)
VCO Tuning Voltage input from the PLL loop
filter. This pin is very sensitive to noise
coupling and leakage currents.
40
SW_CTRL_N
O (CMOS)
TR switch control output, negative polarity.
V
V
OL while transmitting
OH while receiving
-or-
-or-
RXCLK
Recovered RXCLK clock output is multiplexed
in this pin. When configured for RXCLK
output, clock pulses may be observed for 6 to
8uS after the falling edge of RXON before
settling to logic high (VIH).
SERIAL BUS SIGNALS
6
EN
I (CMOS)
Control Bus Enable. Enable pin for the three-
wire serial control bus. The control registers
are loaded on the rising edge of this signal.
Serial control bus data is ignored when this
signal is high (VIH).
7
DATA
I (CMOS)
Serial Control Bus Data.
8
CLK
I (CMOS)
Serial control bus data is clocked in on the
rising edge and only when EN is low.
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PRELIMINARY DATA SHEET
APRIL 2008
EDS-106041 REV P01
7628 THORNDIKE ROAD, GREENSBORO, NC 27409-9421 · FOR SALES OR TECHNICAL
REV A1 DS071026 SUPPORT, CONTACT RFMD AT (+1) 336-678-5570 OR SALES-SUPPORT@RFMD.COM
11
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