欢迎访问ic37.com |
会员登录 免费注册
发布采购

R5F64185PFB 参数 Datasheet PDF下载

R5F64185PFB图片预览
型号: R5F64185PFB
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨MCU [RENESAS MCU]
分类和应用:
文件页数/大小: 124 页 / 1160 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号R5F64185PFB的Datasheet PDF文件第20页浏览型号R5F64185PFB的Datasheet PDF文件第21页浏览型号R5F64185PFB的Datasheet PDF文件第22页浏览型号R5F64185PFB的Datasheet PDF文件第23页浏览型号R5F64185PFB的Datasheet PDF文件第25页浏览型号R5F64185PFB的Datasheet PDF文件第26页浏览型号R5F64185PFB的Datasheet PDF文件第27页浏览型号R5F64185PFB的Datasheet PDF文件第28页  
R32C/118 Group  
2. Central Processing Unit (CPU)  
2.1  
2.1.1  
General Purpose Registers  
Data Registers (R2R0, R3R1, R6R4, and R7R5)  
These 32-bit registers are primarily used for transfers and arithmetic/logic operations.  
Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into  
R2 and R0, R3R0 can be divided into R3 and R1, etc.  
Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and  
R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).  
2.1.2  
Address Registers (A0, A1, A2, and A3)  
These 32-bit registers have functions similar to data registers. They are also used for address register  
indirect addressing and address register relative addressing.  
2.1.3  
Static Base Register (SB)  
This 32-bit register is used for SB relative addressing.  
2.1.4  
Frame Base Register (FB)  
This 32-bit register is used for FB relative addressing.  
2.1.5  
Program Counter (PC)  
This 32-bit counter indicates the address of the instruction to be executed next.  
2.1.6  
Interrupt Vector Table Base Register (INTB)  
This 32-bit register indicates the start address of a relocatable vector table.  
2.1.7  
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)  
Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack  
pointer (ISP).  
Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt  
stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for  
details.  
To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer  
(USP) or the interrupt stack pointer (ISP) to a multiple of 4.  
2.1.8  
Flag Register (FLG)  
This 32-bit register indicates the CPU status.  
2.1.8.1  
Carry Flag (C flag)  
This flag becomes 1 when any of the carry, borrow, shifted-out bit, etc. is generated in the arithmetic  
logic unit (ALU).  
2.1.8.2  
Debug Flag (D flag)  
This flag is only for debugging. Only set this bit to 0.  
2.1.8.3  
Zero Flag (Z flag)  
This flag becomes 1 when the result of an operation is 0; otherwise it is 0.  
2.1.8.4  
Sign Flag (S flag)  
This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.  
REJ03B0255-0100 Rev.1.00 Nov 19, 2009  
Page 24 of 122  
 复制成功!