Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
12. Interrupts
12.3.8
Returning from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved on the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Registers saved by a program in an interrupt routine should be saved using the POPM instruction or a similar
instruction before executing the REIT instruction.
12.3.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select any priority level for maskable interrupts (peripheral function). However, if
two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware,
with the higher priority interrupts acknowledged.
The priority of the watchdog timer and other special interrupts is set by hardware.
Software interrupts are not affected by the interrupt priority. When an instruction is executed, the MCU
executes the interrupt routine.
Reset
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1/comparator A1
Voltage monitor 2/comparator A2
Peripheral function
Single step
Address match
High
Low
Figure 12.7
Hardware Interrupt Priority
REJ09B0441-0010 Rev.0.10
Page 182 of 809
Jul 30, 2008
RENESAS [ RENESAS TECHNOLOGY CORP ]
