R5F2L387BNFP 参数 Datasheet PDF下载

Under development

Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6. Voltage Detection Circuit

6.4

Voltage Monitor 0 Reset

To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter

disabled).

Table 6.3

Step

1

2

3

4

5

6

7

8

Procedure for Setting Bits Associated with Voltage Monitor 0 Reset

When Using Digital Filter

When Using No Digital Filter

Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled).

Wait for td(E-A).

Select the sampling clock of the digital filter by Set the VW0C7 bit in the VW0C register to 1.

bits VW0F1 to VW0F0 in the VW0C register.

Set the VW0C1 bit in the VW0C register to 0

Set the VW0C1 bit in the VW0C register to 1

(digital filter enabled).

(digital filter disabled).

Set the VW0C2 bit in the VW0C register to 0.

Set the CM14 bit in the CM1 register to 0

−

(low-speed on-chip oscillator on).

Wait for 4 cycles of the sampling clock of

−

(No wait time required)

the digital filter.

Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).

Note:

1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction).

VCC

Vdet0

Sampling clock of

digital filter

×

4 cycles

VW0C1 bit is set to 0

(digital filter enabled)

Internal reset signal

1

×

32

fOCO-S

1

×

32

fOCO-S

VW0C1 bit is set to 1

(digital filter disabled)

Internal reset signal

VW0C1 and VW0C7: Bits in VW0C register

The above applies under the following conditions:

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)

• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)

When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized.

When the internal reset signal level changes from low to high,

a program is executed beginning with the address indicated by the reset vector.

Refer to

4. Special Function Registers (SFRs)

for the status of the SFRs after reset.

Figure 6.5

Operating Example of Voltage Monitor 0 Reset

REJ09B0441-0010 Rev.0.10

Page 73 of 809

Jul 30, 2008