R8C/13 Group
12.3 Timer (Timer Z)
12.3 Timer Z
Timer Z is an 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer
Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show the TYZMR,
PREZ, TZSC, TZPR, TYZOC, PUM, and TCSS registers.
Timer Z has the following four operation modes.
• Timer mode: The timer counts internal count source or to count Timer X underflow.
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse.
Data bus
TZSC register
Reload register
TZPR register
Reload register
Reload register
TZCK1 to TZCK0
=00
2
f
f
1
8
=012
Timer Z interrupt
Counter
Counter
=10
=11
2
2
Timer Y underflow
PREZ register
f
2
TZMOD1 to TZMOD0=102, 112
TZS
TZOS
INT0 interrupt
Digital
filter
Input polarity selected to be
one edge or both edges
Polarity
select
INT0
INOSEG
INT0PL
INT0EN
TZOPL=1
TZMOD1 to TZMOD0=01
TZOUT
2, 102, 112
Q
Q
TZOCNT=0
TZOCNT=1
Toggle flip-flop
CLR
CK
P3_1 bit in P3 register
TZOPL=0
Write to TYZMR register
TZMOD1 to TZMOD0 bits=012, 102, 112
Figure 12.18 Timer Z Block Diagram
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TYZMR
Address
008016
After reset
0016
Bit symbol
TYMOD0
Function
0 : Timer mode
Bit name
RW
RW
Timer Y operation
mode bit
1 : Programmable waveform generation mode
0 : Rising edge
1 : Falling edge
INT2/CNTR1 polarity
R1EDG
TYWC
RW
RW
switching bit(1)
Function varies depending on the operation
mode
Timer Y write
control bit
0 : Stops counting
1 : Starts counting
Timer Y count
start flag
TYS
RW
RW
b5 b4
Timer Z operation
mode bit
0 0 : Timer mode
TZMOD0
TZMOD1
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation
mode
RW
RW
RW
Timer Z write
control bit
Function varies depending on the operation
mode
TZWC
Timer Z count
start flag
0 : Stops counting
1 : Starts counting
TZS
NOTES:
1. The IR bit in the INT2IC register may be set to “1” (interrupt requested) when the R1EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
Figure 12.19 TYZMR Register
Rev.1.20 Jan 27, 2006 page 88 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
