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R5F21134DFP 参数 Datasheet PDF下载

R5F21134DFP图片预览
型号: R5F21134DFP
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机M16C族/ R8C / Tiny系列 [16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 224 页 / 2076 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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R8C/13 Group  
12.3 Timer (Timer Z)  
12.3.1 Timer Mode  
In this mode, the timer counts an internally generated count source or Timer Y underflow (see Table  
12.9 Timer Mode Specifications). The TZSC register is unused in timer mode. Figure 12.22 shows  
the TYZMR register and PUM register in timer mode.  
Table 12.9 Timer Mode Specifications  
Item  
Count source  
Count operation  
Specification  
f1, f2, f8, Timer Y underflow  
Down-count  
When the timer underflows, it reloads the reload register contents before continuing  
counting (When the Timer Z underflows, the contents of the Timer Z primary reload  
register is reloaded.)  
Divide ratio  
1/(n+1)(m+1)  
n: set value in PREZ register, m: set value in TZPR register  
Count start condition  
Count stop condition  
Interrupt request  
generation timing  
Write 1(count start) to TZS bit in TYZMR register  
Write 0(count stop) to TZS bit in TYZMR register  
When Timer Z underflows [Timer Z interrupt]  
TZOUT pin function  
Programmable I/O port  
_______  
INT0 pin function  
Read from timer  
Programmable I/O port, or I_N__T__0_ interrupt input  
Count value can be read out by reading TZPR register.  
Same applies to PREZ register.  
Write to timer(1)  
Value written to TZPR register is written to both reload register and counter or written to  
reload register only. Selected by program.  
Same applies to PREZ register.  
NOTES:  
1. The IR bit in the TZIC register is set to "1" (interrupt requested) if you write to the TZPR or PREZ register while both  
of the following conditions are met.  
<Conditions>  
TZWC bit in TYZMR register is set to "0" (write to reload register and counter simultaneously)  
TZS bit in TYZMR register is set to "1" (count start)  
To write to the TZPR or PREZ register in the above state, disable interrupts before the writing.  
Rev.1.20 Jan 27, 2006 page 91 of 205  
REJ09B0111-0120  
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