欢迎访问ic37.com |
会员登录 免费注册
发布采购

R5F21134DFP 参数 Datasheet PDF下载

R5F21134DFP图片预览
型号: R5F21134DFP
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机M16C族/ R8C / Tiny系列 [16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 224 页 / 2076 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号R5F21134DFP的Datasheet PDF文件第91页浏览型号R5F21134DFP的Datasheet PDF文件第92页浏览型号R5F21134DFP的Datasheet PDF文件第93页浏览型号R5F21134DFP的Datasheet PDF文件第94页浏览型号R5F21134DFP的Datasheet PDF文件第96页浏览型号R5F21134DFP的Datasheet PDF文件第97页浏览型号R5F21134DFP的Datasheet PDF文件第98页浏览型号R5F21134DFP的Datasheet PDF文件第99页  
R8C/13 Group  
12.2 Timer (Timer Y)  
Timer Y, Z mode register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
TYZMR  
Address  
008016  
After reset  
0016  
0
Bit symbol  
TYMOD0  
Function  
0 : Timer mode  
RW  
RW  
Bit name  
Timer Y operation  
mode bit  
INT2/CNTR1 polarity  
switching bit(1)  
0 : Rising edge  
1 : Falling edge  
R1EDG  
TYWC  
RW  
0 : Write to reload register and counter  
simultaneously  
1 : Write to reload register  
Timer Y write  
control bit(2)  
RW  
RW  
0 : Stops counting  
1 : Starts counting  
Timer Y count  
start flag  
TYS  
Timer Z-related bit  
TZMOD0  
TZMOD1  
RW  
RW  
TZWC  
TZS  
RW  
RW  
NOTES:  
1. The IR bit in the INT2IC register may be set to 1(interrupt requested) when the R1EDG bit is rewritten.  
Refer to the paragraph 1.2.5 Changing Interrupt Factorin the Usage Notes Reference Book.  
2. When TYS bit= 1 (starts counting), the value set in the TYWC bit is valid. If TYWC bit=0, the timer Y count value is  
written to both reload register and counter. If TYWC bit=1, the timer Y count value is written to the reload register  
only. When TYS bit=0 (stops counting), the timer Y count value is written to both reload register and counter  
regardless of how the TYWC bit is set.  
Timer Y, Z waveform output control register  
b7 b6 b5 b4 b3 b2 b1 b0  
Symbol  
PUM  
Address  
008416  
After reset  
0016  
0
0 0 0  
Bit symbol  
Bit name  
Reserved bit  
Function  
RW  
RW  
Must set to 0”  
(b3-b0)  
TYOPL  
Timer Y output level  
latch  
Invalid in timer mode  
RW  
TZOPL  
Timer Z-related bits  
RW  
RW  
INOSTG  
INOSEG  
RW  
Figure 12.15 TYZMR Register and PUM Register in Timer Mode  
Rev.1.20 Jan 27, 2006 page 84 of 205  
REJ09B0111-0120  
 复制成功!