R8C/13 Group
12.2 Timer (Timer Y)
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUM
Address
008416
After reset
0016
0
0 0 0
Bit symbol
Bit name
Reserved bit
RW
RW
Function
Must set to “0”
(b3-b0)
TYOPL
Timer Y output level
latch
Function varies depending on the operation mode
Function varies depending on the operation mode
RW
Timer Z output level
latch
TZOPL
RW
RW
INT0 pin one-shot trigger
control bit(2)
(Timer Z)
0 : INT0 pin one-shot trigger invalid
1 : INT0 pin one-shot trigger valid
INOSTG
INOSEG
INT0 pin one-shot trigger
polarity select bit(1)
(Timer Z)
0 : Edge trigger at falling edge
1 : Edge trigger at rising edge
RW
NOTES:
1. The INOSEG bit is valid only when the INT0PL bit in the INTEN register is "0" (one-edge).
2. The INOSGT bit must be set to "1" after the INT0EN bit in the INTEN register and the INOSEG bit in the PUM register
are set.
Timer count source setting register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TCSS
Address
008E16
After reset
0016
0
0
RW
RW
Bit symbol
TXCK0
Bit name
Function
b1 b0
Timer X count source
select bit(1)
0 0 : f
0 1 : f
1
8
1 0 : f32
TXCK1
TYCK0
RW
RW
RW
RW
RW
RW
1 1 : f
2
b3 b2
Timer Y count source
select bit(1)
0 0 : f
0 1 : f
1
8
1 0 : fRING
1 1 : Selects input from CNTR1 pin
TYCK1
TZCK0
b5 b4
Timer Z count source
select bit(1)
0 0 : f
0 1 : f
1
8
1 0 : Selects Timer Y underflow
1 1 : f
TZCK1
(b7-b6)
2
Reserved bit
Must be set to “0”
NOTES:
1. Avoid switching a count source, while a counter is in progress. Timer counter must be stopped before switching a count
source.
Figure 12.14 PUM Register and TCSS Register
Rev.1.20 Jan 27, 2006 page 82 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
