R8C/13 Group
12.1 Timer (Timer X)
12.1.2 Pulse Output Mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode
Specifications”). Figure 12.5 shows TXMR register in pulse output mode.
Table 12.3 Pulse Output Mode Specifications
Item
Count source
Count operation
Specification
f1, f2, f8, f32
• Down-count
•
When the timer underflows, the contents in the reload register is reloaded and the count
is contiuned.
Divide ratio
1/(n+1)(m+1)
n: set value of PREX register, m: set value of TX register
Count start condition
Count stop condition
Interrupt request
Write “1” (count start) to TXS bit in TXMR register
Write “0” (count stop) to TXS bit in TXMR register
• When Timer X underflows [Timer X interruption]
generation timing
INT1/CNTR0 pin function
CNTR0 pin function
Read from timer
Pulse output
Programmable I/O port or inverted output of CNTR0
Count value can be read by reading TX register.
Same applies to PREX register.
Write to timer
Value written to TX register is written to both reload register and counter.
Same applies to PREX register.
Select function
• I_N__T__1/CNTR0 polarity switching function
Polarity level at starting of pulse output can be selected with R0EDG bit(1)
• Inverted pulse output function
___________
Inverted pulse of CNTR0 output polarity can be output from the CNTR0 pin
(selected by TXOCNT bit)
NOTES:
1. The level of the output pulse becomes the level when the pulse output starts when the TX register is written to.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TXMR
Address
008B16
After reset
0016
1
0
0
0 0
Bit symbol
TXMOD0
TXMOD1
Function
0 1 : Pulse output mode
RW
RW
RW
Bit name
b1 b0
Operation mode
select bit 0, 1
INT1/CNTR0 polarity
0: CNTR
1: CNTR
0
0
output starts at "H"
output starts at "L"
R0EDG
RW
RW
RW
RW
switching bit(1)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
TXS
P30
/CNTR
0
0 : Port P3
1 : CNTR
0
TXOCNT
select bit
0
output
TXMOD2
Set to "0" in pulse output mode
Set to "0" in pulse output mode
Set to "0" in pulse output mode
TXEDG
TXUND
RW
RW
NOTES:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
Figure 12.5 TXMR Register in Pulse Output Mode
Rev.1.20 Jan 27, 2006 page 74 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
