R8C/13 Group
10.1 Interrupt Overview
• Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits in the PC are saved.
Figure 10.6 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine.
(1)
The PUSHM instruction can save several registers in the register bank being currently used with a
single instruction .
NOTES:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Stack
Stack
Address
MSB
Address
MSB
LSB
LSB
[SP]
New SP value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
PC
L
PC
M
FLG
L
FLG
H
PCH
[SP]
SPvalue before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request
The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving
registers.
NOTES:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indi-
cated by the U flag. Otherwise, it is the ISP.
Address
Stack
Sequence in which order
registers are saved
[SP] – 5
[SP] – 4
[SP] – 3
[SP] – 2
PC
PC
L
(3)
(4)
M
Saved, 8 bits at a time
FLG
L
(1)
(2)
FLG
H
PC
H
[SP] – 1
[SP]
Finished saving registers
in four operations.
NOTES:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 10.7 Operation of Saving Register
Rev.1.20 Jan 27, 2006 page 57 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
