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R8C/13 Group
10.2 INT Interrupt
10.2 _I_N__T__ Interrupt
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10.2.1 INT0 Interrupt
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INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN
register must be set to “1” (enabling). The edge polarity is selected using the INT0PL bit in the INTEN
register and the POL bit in the INT0IC register.
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The INT0 pin is shared with the external trigger input pin of Timer Z.
Figure 10.10 shows the INTEN and INT0F registers.
External input enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INTEN
Address
009616
After reset
0016
0
0
0
0
0
0
Bit symbol
RW
RW
Bit name
Function
INT0 input enable bit(1)
INT0EN
0 : Disabled
1 : Enabled
INT0 input polarity select bit(2)
Reserved bit
INT0PL
0 : One edge
1 : Both edges
RW
RW
Set to “0”
(b7-b2)
NOTES:
1. This bit must be set while the INT0STG bit in the PUM register is set to “0” (one-shot trigger disabled).
2. When setting the INT0PL bit to “1” (selecting both edges), the POL bit in the INT0IC must be set to “0”
(selecting falling edge).
3. The IR bit in the INT0IC register may be set to “1” (interrupt requested) when the INT0PL bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
INT0 input filter select register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT0F
Address
001E16
After reset
XXXXX0002
Bit symbol
RW
Bit name
Function
b1 b0
INT0 input filter select bit
INT0F0
INT0F1
(b2)
RW
0 0 : No filter
0 1 : Filter with f1 sampling
1 0 : Filter with f8 sampling
1 1 : Filter with f32 sampling
RW
RW
Reserved bit
Set to “0”
Nothing is assigned.
When write, set to “0”. If read, it content is indeterminate.
(b7-b3)
Figure 10.10 INTEN and INT0F Registers
Rev.1.20 Jan 27, 2006 page 60 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
