R8C/13 Group
10.1 Interrupt Overview
10.1.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec-
tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in
the corresponding interrupt vector. Figure 10.2 shows the interrupt vector.
MSB
LSB
Low address
Mid address
Vector address (L)
0 0 0 0
0 0 0 0
High address
0 0 0 0
Vector address (H)
(Note 1)
NOTES:
1. The OFS register is assigned to the 0FFFF16 address. Refer to "Figure11.2
OFS, WDC, WDTR and WDTS registers" for the OFS register details.
Figure 10.2 Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from 0FFDC16 to 0FFFF16. Table 10.1 lists
the fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of
fixed vectors are used by the ID code check function. For details, refer to Section 17.3, “Functions to
Prevent Flash Memory from Rewriting.”
Table 10.1 Fixed Vector Tables
Interrupt factor
Vector addresses
Remarks
Reference
Address (L) to address (H)
Undefined instruction 0FFDC16 to 0FFDF16
Interrupt on UND instruction
Interrupt on INTO instruction
R8C/Tiny Series
software manual
Overflow
0FFE016 to 0FFE316
0FFE416 to 0FFE716
If the contents of address
0FFE716 is FF16, program ex-
ecution starts from the address
shown by the vector in the
relocatable vector table.
BRK instruction
Address match
0FFE816 to 0FFEB16
18.1 Address match
interrupt
(1)
Single step
0FFEC16 to 0FFEF16
0FFF016 to 0FFF316
• Watchdog timer
• Oscillation stop
detection
11. Watchdog timer
6. Clock generation
circuit
• Voltage detection
5.4Voltage detection
circuit
(Reserved)
(Reserved)
Reset
0FFF416 to 0FFF716
0FFF816 to 0FFFB16
0FFFC16 to 0FFFF16
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development support tools.
Rev.1.20 Jan 27, 2006 page 50 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
