R8C/13 Group
9. Bus
9. Bus
During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for
access space.
The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16
bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access
space.
Table 9.1 Bus Cycles for Access Space
Access space
SFR/Data flash
Bus cycle
2 CPU clock cycles
Program ROM/RAM 1 CPU clock cycles
Table 9.2 Access Unit and Bus Operation
Space
SFR, Data flash
Program ROM/RAM
Even address
byte access
CPU clock
CPU clock
Address
Address
Even
Even
Data
Data
Data
Data
CPU clock
Odd address
byte access
CPU clock
Address
Address
Odd
Odd
Data
Data
Data
Data
Even address
word access
CPU clock
CPU clock
Address
Data
Address
Even
Data
Even+1
Data
Even+1
Even
Data
Data
Data
Odd address
word access
CPU clock
CPU clock
Address
Data
Address
Odd
Odd+1
Data
Odd
Data
Odd+1
Data
Data
Data
Rev.1.20 Jan 27, 2006 page 46 of 205
REJ09B0111-0120
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