R8C/13 Group
6.5 Oscillation Stop Detection Function
6.5 Oscillation Stop Detection Function
The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The
oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the OCD
register.
Table 6.4 lists the specifications of the oscillation stop detection function.
Where the main clock corresponds to the CPU clock source and the OCD1 to OCD0 bits are “112”
(oscillation stop detection function enabled), the system is placed in the following state if the main clock
comes to a halt:
• OCD register OCD2 bit = 1 (selecting on-chip oscillator clock)
• OCD register OCD3 bit = 1 (main clock stopped)
• CM1 register CM14 bit = 0 (low-speed on-chip oscillator oscillating)
• Oscillation stop detection interrupt request occurs
Table 6.4 Oscillation Stop Detection Function Specifications
Item
Specification
Oscillation stop detectable clock and
frequency bandwidth
f(XIN) ≥ 2 MHz
Enabling condition for oscillation stop Set OCD1 to OCD0 bits to “11
2
” (oscillation stop detection
detection function function enabled)
Operation at oscillation stop detection Oscillation stop detection interrupt occurs
6.5.1 How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. If the
oscillation stop detection and watchdog timer interrupts both are used, the interrupt factor must be
determined. Table 6.5 shows how to determine the interrupt factor with the oscillation stop detection
interrupt, watchdog timer interrupt and voltage detection interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and
peripheral functions must be switched to the main clock in the program.
Figure 6.7 shows the procedure for switching the clock source from the low-speed on-chip oscillator
to the main clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to “0” (periph-
eral function clocks not turned off during wait mode).
• Since the oscillation stop detection function is provided in preparation for main clock stop due to
external factors, set the OCD1 to OCD0 bits to “002” (oscillation stop detection function disabled)
where the main clock is stopped or oscillated in the program, that is where the stop mode is selected
or the CM05 bit is altered.
• This function cannot be used when the main clock frequency is below 2 MHz. Set the OCD1 to OCD0
bits to “002” (oscillation stop detection function disabled).
• When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral
functions after detecting the oscillation stop, set the HR01 bit in the HR0 register to “0” (low-speed
on-chip oscillator selected) and the OCD1 to OCD0 bits to “112” (oscillation stop detection function
enabled). When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of
peripheral functions after detecting the oscillation stop, set the HR01 bit to “1” (high-speed on-chip
oscillator selected) and the OCD1 to OCD0 bits to “112” (oscillation stop detection function enabled).
Rev.1.20 Jan 27, 2006 page 42 of 205
REJ09B0111-0120
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