R8C/13 Group
19. Usage Notes
19.2 Interrupt
19.2.1 Reading Address 0000016
Do not read the address 0000016 by a program. When a maskable interrupt request is acknowledged,
the CPU reads interrupt information (interrupt number and interrupt request level) from 0000016 in the
interrupt sequence. At this time, the acknowledged interrupt IR bit is set to “0”.
If the address 0000016 is read by a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to “0”. This may cause a problem that the interrupt is canceled, or
an unexpected interrupt is generated.
19.2.2 SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to “000016” after reset.
Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out
of control.
19.2.3 External Interrupt and Key Input Interrupt
________
Either an “L” level or an ”H” level of at least 250ns width is necessary for the signal input to the INT0 to
________
_____
_____
INT3 pins and KI0 to KI3 pins regardless of the CPU clock.
19.2.4 Watchdog Timer Interrupt
Reset the watchdog timer after a watchdog timer interrupt is generated.
Rev.1.20 Jan 27, 2006 page 188 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
