R8C/13 Group
15. Programmable I/O Ports
Table 15.13 Port P14/TXD0 Setting
Register
Bit
PD1 PUR0 DRR
U0MR
U0C0
Function
PD1_4 PU03 DRR4 SMD2, SMD0 NCH
0
0
1
1
0
1
X
X
0
1
002
002
002
002
X1
1X
X1
1X
X1
1X
X1
1X
X
X
X
X
Input port (not pulled up)
Input port (pulled up)
Output port
X
X
Output port (High drive)
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
TXD0 output, CMOS output
Setting value
TXD0 output, CMOS output (High drive)
T
X
X
D
0
0
output, N-channel open output
T
D
output, N-channel open output (High drive)
X: “0” or “1”
Table 15.14 Port P15/RXD0 Setting
Register
Bit
PD1 PUR0 DRR
PD1_5 PU03 DRR5
Function
0
0
0
1
1
0
1
0
X
X
X
X
X
0
Input port (not pulled up)
Input port (pulled up)
RXD0 input
Setting value
Output port
1
Output port (High drive)
X: “0” or “1”
Table 15.15 Port P16/CLK0 Setting
Register
Bit
PD1 PUR0 DRR
U0MR
Function
PD1_6 PU03 DRR6 SMD2, SMD0, CKDIR
0
0
0
1
1
X
X
0
1
X
X
X
0
1
0
1
Other than 0102
Other than 0102
XX1
Input port (not pulled up)
Input port (pulled up)
0
CLK0 (external clock) input
Output port
Setting value
X
X
X
X
Other than 0102
Other than 0102
0102
Output port (High drive)
CLK0 (internal clock) output
CLK0 (internal clock) output (High drive)
0102
X: “0” or “1”
Rev.1.20 Jan 27, 2006 page 148 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
