R1LV0408C-C Series
Low VCC Data Retention Characteristics
(Ta = −20 to +70°C)
Parameter
Symbol Min Typ Max Unit Test conditions*3
VCC for data retention
VDR
2
8
V
CS# ≥ VCC − 0.2 V, Vin ≥ 0 V
Data
−5SC
to +70°C
to +40°C
to +25°C
to +70°C
to +40°C
to +25°C
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
tCDR
0
µA VCC = 3.0 V, Vin ≥ 0 V
retention
current
0.7*2
0.5*1
0.7*2 10
0.5*1 10
3
µA CS# ≥ VCC − 0.2 V
3
µA
µA
µA
µA
−7LC
16
Chip deselect to data retention time
Operation recovery time
ns
ns
See retention waveform
tR
t
RC*4
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS# Controlled)
tR
tCDR
Data retention mode
VCC
2.7 V
2.2 V
VDR
CS#
0 V
CS# ≥ VCC – 0.2 V
Rev.2.00, May.25.2004, page 12 of 12
RENESAS [ RENESAS TECHNOLOGY CORP ]
