2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle( W# control mode )
A
0~18
(Word Mode)
t
CW
A
-1~18
(Byte Mode)
t
su
(BC1) or
t
su
(BC2)
BC1#,
BC2#
(Note5)
(Note5)
S1#
(Note5)
t
su
(S1)
(Note5)
S2
(Note5)
t
su
(S2)
(Note5)
OE#
t
su
(A)
W#
DQ
1~16
(Word Mode)
t
su
(A-WH)
t
w
(W)
t
dis
(W)
t
rec
(W)
t
en
(OE)
t
en
(W)
t
dis
(OE)
DATA IN
STABLE
DQ
1~8
(Byte Mode)
t
su
(D)
t
CW
t
h
(D)
Write cycle (BC# control mode)
A
0~18
(Word Mode)
A
-1~18
(Byte Mode)
BC1#,
BC2#
S1#
(Note5)
t
su
(A)
t
su
(BC1) or
t
su
(BC2)
t
rec
(W)
(Note5)
S2
(Note5)
(Note7)
(Note6)
(Note5)
(Note5)
W#
DQ
1~16
(Word Mode)
t
su
(D)
DATA IN
STABLE
t
h
(D)
(Note5)
DQ
1~8
(Byte Mode)
Note 5: Hatching indicates the state is "don't care".
Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low.
Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of
S1# or rising edge of S2, the outputs are maintained in the high impedance state.
Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
7
RENESAS [ RENESAS TECHNOLOGY CORP ]
