2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W817KT is organized as 524288-words by 16-
bit / 1048576-words by 8-bit. These dev ices operate on a
single +2.7~3.6V power supply , and are directly TTL
compatible to both input and output. Its f ully static circuit
needs no clocks and no ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S1#, S2 , W#,
OE# and BY TE#. Each mode is summarized in the f unction
table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S1# and the high lev el S2. The address (A-1~A18 :
By te mode, A0~A18 : Word mode) must be set up bef ore
the write cy c le and must be stable during the entire cy cle.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S1#and S2 are in an activ e state (S1#=L, S2=H).
When setting BYTE# at a low lev el, the f unction will be
in the x8 mede, which is, DQ1-8 are av ailable and DQ9-16
are not av ailable. In the x8 mode, A-1 is used as the
additional address. During the activ e f unction f or x8 mode,
BC1# BC2# must be low lev el.
When setting BC1# and BC2# at a high lev el or S1# at
a high lev el or S2 at a low lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by
BC1#, BC2# and S1#, S2.
The power supply c urrent is reduced as low as 0.1µA
(25°C, ty pical), and the memory data can be held at +2.0V
power supply , enabling battery back-up operation during
power f ailure or power-down operation in the non-selected
mode.
FUNCTION TABLE
S1#
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
S2
H
L
X
H
H
H
H
H
H
H
H
H
H
H
H
BYTE# BC1# BC2#
H or L
H or L
H
H
H
H
H
H
H
H
H
H
L
L
L
X
X
H
L
L
L
H
H
H
L
L
L
L
L
L
X
X
H
H
H
H
L
L
L
L
L
L
L
L
L
W#
X
X
X
L
H
H
L
H
H
L
H
H
L
H
H
OE#
X
X
X
X
L
H
X
L
X
X
L
X
X
L
H
Mode
Non selection
Non selection
Non selection
Write
Read
-------
Write
Read
-------
Write
Read
-------
Write
Read
-------
DQ1~8 DQ9~15
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
DQ16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
A-1
A-1
A-1
Icc
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Note1 : "H" and "L" in this table mean V
IH
and V
IL,
respectiv ely .
Note2 : "X" in this table should be "H" or "L".
2
RENESAS [ RENESAS TECHNOLOGY CORP ]
