2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta=-40~+85ºC, Vcc=2.7V~3.6V,unless otherwise noted)
(1) TEST CONDITIONS
2.7~3.6V
Input pulse
V
IH
=2.7V, V
IL
=0.2V
Input rise time and f all time
5ns
Supply v oltage
Ref erence lev el
Output loads
1TTL
DQ
CL
Including scope and
jig capacitance
V
OH
=V
OL
=1.5V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol
t
CR
t
a
(A)
t
a
(S1)
t
a
(S2)
t
a
(BC1)
t
a
(BC2)
t
a
(OE)
t
dis
(S1)
t
dis
(S2)
t
dis
(BC1)
t
dis
(BC2)
t
dis
(OE)
t
en
(S1)
t
en
(S2)
t
en
(BC1)
t
en
(BC2)
t
en
(OE)
t
V
(A)
Parameter
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1# high
Output disable time af t er S2 low
Output disable time af t er BC1# high
Output disable time af t er BC2# high
Output disable time af t er OE# high
Output enable time af ter S1# low
Output enable time af ter S2 high
Output enable time af ter BC1# low
Output enable time af ter BC2# low
Output enable time af ter OE# low
Data v alid time after address
Limits
70HI
Min
70
Max
70
70
70
70
70
35
25
25
25
25
25
10
10
5
5
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
(3) WRITE CYCLE
Symbol
Parameter
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W#
By te control 1 setup time
By te control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recov ery time
Output disable time f rom W# low
Output disable time f rom OE# high
Output enable time f rom W# high
Output enable time f rom OE# low
Limits
70HI
Min
70
55
0
65
65
65
65
65
35
0
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(BC1)
t
su
(BC2)
t
su
(S1)
t
su
(S2)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
25
25
5
5
5
RENESAS [ RENESAS TECHNOLOGY CORP ]
