2002.08.30
Ver. 6.1
MITSUBISHI LSIs
M5M5W816TP - 55HI, 70HI, 85HI
FUNCTION
The M5M5W816TP is organized as 524288-words by 16-
bit. These dev ices operate on a single +2.7~3.6V power
supply , and are directly TTL compatible to both input and
output. Its f ully s t atic circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1# , BC2# , S# , W# and
OE#. Each mode is summarized in the f unction table.
A write operation is executed whenev er the low lev el W#
ov erlaps with the low lev el BC1# and/or BC2# and the low
lev el S#. The address(A0~A18) must be set up bef ore the
write cy c le and must be stable during the entire cy c le.
A read operation is executed by s etting W# at a high
lev el and OE# at a low lev el while BC1# and/or BC2# and
S# are in an activ e state(S#=L).
When setting BC1# at the high lev el and other pins are
in an activ e stage , upper-by t e are in a selectable mode in
which both reading and writing are enabled, and lower-by t e
are in a non-selectable mode. And when setting BC2# at a
high lev el and other pins are in an activ e stage, lower-
by t e are in a selectable mode and upper-by te are in a
non-selectable mode.
8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
When setting BC1# and BC2# at a high lev el or S# at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with other
chips and memory expansion by BC1#, BC2# and S#.
The power supply c urrent is reduced as low as 0.1µA(25°C,
ty pical), and the memory data can be held at +2.0V power
supply , enabling battery back-up operation during power
f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S#
BC1# BC2#
W# OE#
Mode
Non selection
Non selection
DQ1~8 DQ9~16
Icc
H
X
L
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
L
L
X
X
L
H
H
L
H
H
L
H
H
X
X
X
L
H
X
L
H
X
L
H
Write
Read
Write
Read
Write
Read
High-Z
High-Z
Din
Dout
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
High-Z Standby
High-Z Standby
High-Z Activ e
High-Z Activ e
High-Z Activ e
Din
Activ e
Dout
Activ e
High-Z Activ e
Din
Activ e
Dout
Activ e
High-Z Activ e
BLOCK DIAGRAM
A
0
A
1
MEMORY ARRAY
524288 WORDS
x 16 BITS
A
17
A
18
(note) "H" and "L" in this table mean V
IH
or V
IL
, respectiv ely .
"X" in this table should be "H"or "L".
DQ
1
DQ
8
-
DQ
9
CLOCK
GENERATOR
S#
DQ
16
BC1#
BC2#
Vcc
W#
GND
OE#
2
RENESAS [ RENESAS TECHNOLOGY CORP ]
