MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
(1) when data other than “D016” and “FF16” is written to the data in
the 2nd bus cycle of the block erase command (2016/D016)
(2) when data other than “2016” and “FF16” is written to the data in
the 2nd bus cycle of the erase all block command
(2016/2016)
Erase Status Bit (SR.5)
This bit reports the status of the automatic erase operation. This bit
is set to “1” if an erase error occurs and returns to “0” if the clear sta-
tus register command (5016) is written.
Programming Status Bit (SR.4)
Note that, writing of “FF16” forces the microcomputer into the read
array mode. Simultaneously with this, the command written in the 1st
bus cycle will be canceled.
This bit reports the status of the automatic programming operation.
This bit is set to “1” if a programming error occurs and returns to “0”
if the clear status register command (5016) is written.
Under the condition that any of SR.5, SR.4 = “1”, none of the pro-
gramming, block erase, and erase all block commands can be ac-
cepted. Before execution of these commands, execute the clear
status register command (5016), in advance, to clear these status
bits.
Full Status Check
The full status check reports the results of the erase or programming
operation.
Figure 11 shows the full status check flowchart and actions to be
taken if an error has occurred.
Both of SR.4, SR.5 are set to “1” under the following conditions
(Command Sequence Error):
Table 3. Bit definition of status register
Definition
Status
Symbol
“0”
“1”
Reserved
SR.7 (D7)
SR.6 (D6)
SR.5 (D5)
SR.4 (D4)
SR.3 (D3)
SR.2 (D2)
SR.1 (D1)
SR.0 (D0)
Reserved
Erase Status
Terminated by error.
Terminated by error.
Terminated normally.
Terminated normally.
Programming Status
Reserved
Reserved
Reserved
Reserved
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