MITSUBISHI MICROCOMPUTERS
M37905F8CFP, M37905F8CSP
16-BIT CMOS MICROCOMPUTER
Function overview (CPU reprogramming mode)
The CPU reprogramming mode is available in the single-chip mode,
memory expansion mode, and boot mode to reprogram the user
ROM area only.
chart, and be sure to follow this flowchart. As shown in Note 1 of Fig-
ure 8, before selecting the CPU reprogramming mode, set “0” to the
processor mode register 1’s bit 7 (the internal ROM bus cycle select
bit) and set flag I to “1” to avoid an interrupt request input.
When a watchdog timer interrupt request is generated in the CPU
reprogramming mode, when an input to the RESET pin is “L”, or
when the software reset is performed, the flash memory control cir-
cuit and flash memory control register will be reset.
In the CPU reprogramming mode, the CPU erases, programs, and
reads the internal flash memory by writing software commands. Note
that the user-original reprogramming control software must be trans-
ferred to the internal RAM in advance to be executed.
The CPU reprogramming mode becomes active when “1” is written
into the flash memory control register’s bit 1 (the CPU reprogram-
ming mode select bit) shown in Figure 7, and software commands
become acceptable.
When the flash memory is reset during the erase or programming
operation, this operation is cancelled and the target block’s data will
be invalid. Just before writing a software command related to the
erase/programming operation, be sure to write to the watchdog
timer. In the CPU reprogramming mode, be sure not to use the STP
and WIT instructions.
In the CPU reprogramming mode, software commands and data are
all written to and read from even addresses (Note that address A0 in
byte addresses = “0”.) 16 bits at a time. Therefore, a software com-
mand consisting of 8 bits must be written to an even address; there-
fore, any command written to an odd address will be invalid. Since
the write data at the 2nd cycle of a programming command consists
of 16 bits, this data must be written to even and odd addresses.
The seaquencer in the flash memory controls the erase and pro-
gramming operations. What the status of the seaquencer operation
is and whether the programming or erase operation has been com-
pleted normally or terminated by an error can be examined by read-
ing the flash memory control register.
Figure 7 shows the bit configuration of the flash memory control reg-
ister.
Bit 0 (the RY/BY status bit) is a read-only bit for indicating the sea-
quencer operation. This bit goes to “0” (BUSY) while the automatic
programming/erase operation is active and goes to “1” (READY) dur-
ing the other operations.
Bit 1 serves as the CPU reprogramming mode select bit. Writing of
“1” to this bit selects the CPU reprogramming mode, and software
commands will be acceptable. Because the CPU cannot directly ac-
cess the internal flash memory in the CPU reprogramming mode,
writing to this bit 1 must be performed by the user-original repro-
gramming control software which has been transferred to the inter-
nal RAM in advance. To set bit 1 to “1”, it is necessary to write “0” and
“1” to this bit 1 successively. On the other hand, to clear this bit to “0”,
it is sufficient only to write “0”.
Bit 3 (the flash memory reset bit) resets the control circuit of the in-
ternal flash memory and is used when the CPU reprogramming
mode is terminated or when an abnormal access to the flash
memory happens. Writing of “1” to bit 3 with the CPU reprogramming
mode select bit = “1” preforms the reset operation. To remove the
reset, write “0” to bit 3 after confirming bit 0 (the RY/BY status bit) be-
comes “1”.
Bit 5 serves as the user ROM area select bit and is valid only in the
boot mode. Setting this bit to “1” in the boot mode switches an acces-
sible area from the boot ROM area to the user ROM area. To use the
CPU reprogramming mode in the boot mode, set this bit to “1”. Note
that when the microcomputer is booted up in the user ROM area,
only the user ROM area is accessible and bit 5 is invalid; on the other
hand, when the microcomputer is in the boot mode, bit 5 is valid in-
dependent of the CPU reprogramming mode. To rewrite bit 5, ex-
ecute the user-original reprogramming control software transferred
to the internal RAM in advance.
Figure 8 shows the CPU reprogramming mode set/termination flow-
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RENESAS [ RENESAS TECHNOLOGY CORP ]
